Near-Perfect on Paper: Diamond Semiconductors Are Missing One n-Type Layer

On paper, diamond looks like the final answer in semiconductor materials. Bandgap 5.47 eV, breakdown field around 10 MV/cm, theoretical electron and hole mobilities of 4,500 and 3,800 cm²/(V·s), thermal conductivity 2,200 W/(m·K), dielectric constant of just 5.5. Any one of those figures would make silicon, SiC and GaN look ordinary.

But it carries one defect nobody has solved: there is no usable n-type doping. Without a stable n-type conductive layer, you cannot build a PN junction, and without a PN junction you cannot build CMOS logic. So in the near term diamond cannot "replace silicon" as a computing chip. Its realistic role is first of all a heat-spreading substrate, not a logic element.

1. First, how extreme those numbers are

Breakdown field is the parameter that matters most in a power device. 10 MV/cm is 3.6 times that of SiC - at the same blocking voltage the drift layer can be thinner, and on-resistance falls with it. That is the underlying arithmetic of power devices: blocking voltage is bought with thickness, and thickness is resistance.

On the Johnson figure of merit, which captures high-frequency and high-voltage capability together, diamond reaches about 200 V/ps against roughly 90 for SiC - 2.2 times. And at 22 W/(cm·K), junction temperature stays under control even at extreme power density.

One caveat: these figures apply only to single-crystal diamond (SCD). Polycrystalline diamond (PCD) suffers from grain-boundary defects and loses an order of magnitude electrically - reported PCD Schottky diodes break down at only 0.25 MV/cm. When the industry says "diamond semiconductor," it always means single crystal. Polycrystalline diamond is fit for heat spreaders and wear parts, nothing more.

2. The shortfall sits in that one n-type layer

Diamond's doping problem is half easy, half brutal.

p-type is manageable. Boron is the standard acceptor, with an activation energy of about 0.37 eV, and it has been made practical. That is why nearly all early diamond devices were p-channel devices or p-type Schottky diodes.

n-type is the wall. Phosphorus is the most promising donor, but its activation energy is 0.6 eV - far above the ~0.026 eV available from room-temperature thermal energy, so ionization efficiency is very low and carrier concentration never builds. Geometry makes it worse: a phosphorus atom measures 0.110 nm against carbon's 0.077 nm, so inserting it distorts the lattice. And doping efficiency on the (001) plane is one to two orders of magnitude lower than on (111) - and (001) is exactly the plane large-area epitaxy relies on.

Nitrogen is worse still, with an activation energy of 1.4–1.7 eV; at room temperature it is essentially an insulator and does not even qualify as a fallback.

No electrons means no n-type. No n-type means no PN junction. No PN junction means no CMOS. Each link depends on the one before it.

3. Four ways around the wall

The industry is not waiting for an n-type breakthrough. It is pursuing routes that avoid bulk doping altogether:

1. Co-doping: boron–hydrogen–phosphorus co-doping has already delivered electron concentrations of 1×10¹⁹ cm^-3 at a resistivity of 0.249 Ω·cm - one of the more promising results to date;
2. Surface termination: hydrogen-terminated diamond forms a two-dimensional hole gas (2DHG) that conducts without any bulk doping, and is today's workhorse structure for RF devices;
3. Surface adsorption doping: NO₂ adsorption combined with Al₂O₃ passivation substantially raises the current and frequency performance of hydrogen-terminated FETs;
4. Heterojunctions: instead of fighting diamond's own lattice, pair it with another n-type material. In 2024 the Ningbo Institute of Materials Technology and Engineering (CAS) built a p-diamond / n-Ga₂O₃ heterojunction PN diode that blocked over 3,000 V with no edge termination, with an interfacial thermal conductance of 42 MW/(m²·K).

Each route has its price: co-doping mechanisms are complicated, terminated surfaces are sensitive to process contamination, heterojunctions must handle lattice mismatch. But together they prove one point - diamond does not have to become silicon before it can become a device.

4. Devices are already running

• Schottky barrier diodes: in 2025 a University of Florida team built Al-based SBDs on p/p⁺ vertical SCD and reached about 700 V with no edge termination at all, an on-resistance of 16.6 mΩ·cm², a power figure of merit of 30.5 MW/cm² and a reverse recovery time of 7.6 ns;
• p-channel MOSFETs: NIMS in Japan built normally-off devices on a 150 nm boron-doped epitaxial layer with a blocking voltage above 1.7 kV and a breakdown field of 1.52 MV/cm - more than double earlier devices of the same class;
• n-channel MOSFETs: in 2024 the NIMS team led by Satoshi Koizumi used MPCVD for precise phosphorus doping to demonstrate the world's first n-channel diamond MOSFET, with a field-effect mobility of about 150 cm²/(V·s) at 300 °C - the first time diamond CMOS had a materials foundation;
• Real power conversion: a Japanese start-up spun out of Waseda University achieved 550 V / 0.8 A in a single device in March 2026 and completed 200 V · 1 A continuous switching, then showed the first DC/DC buck converter driven by diamond MOSFETs. In April it demonstrated a monolithic bidirectional diamond switch using a hydrogen-terminated 2DHG channel, cutting on-resistance to 8.2 mΩ·cm² - an order of magnitude below deep-depletion structures. The company has begun space validation with JAXA and targets commercialisation in the 2030s;
• RF: NIMS used NO₂ adsorption doping plus Al₂O₃ passivation to reach a drain current of −1.35 A/mm (a record for diamond FETs), a cutoff frequency of 35 GHz, a maximum oscillation frequency of 70 GHz and an output power density of 2 W/mm at 1 GHz.

Read together, the significance of 2025–2026 is this: diamond power devices have moved from materials research into device validation.

5. Two more hurdles: substrates and process infrastructure

Substrate size and cost. SCD mainstream is still 2-inch, reproducible 3-inch processing has only just been established, while SiC already runs 8-inch volume production. On price, a 2-inch electronic-grade SCD wafer cost roughly US$3,200 in 2025 and is projected to fall to about US$1,500 by the early 2030s - still tens of times SiC. Japan's Orbray uses step-flow growth on sapphire to reach 2-inch in 2021, and in 2026 established reproducible 3-inch processing with UK-based Element Six, with 4-inch in development.

Process infrastructure. Diamond is too hard for conventional CMP, and etching and ion implantation are not yet mature. There is no complete equipment set or process library. No single company can fix that; it takes the whole supply chain.

The global build-out is already visible. In Japan, NIMS leads on n-type and RF work, while a start-up founded by Hokkaido University and AIST built the world's first diamond semiconductor fab in Fukushima in 2026, with lab yield above 90%, volume production planned for FY2028 and about ¥7.4 billion raised. In Europe, Element Six and Orbray pursue the 3-inch route, a CNRS spin-out opened Europe's first diamond semiconductor pilot line in Grenoble in 2026 on €8.7 million, and the Spanish government committed €753 million to Diamond Foundry for a diamond microchip plant. In the US, the GaN-on-Diamond approach transfers GaN epilayers onto CVD diamond substrates and runs 65–70 °C cooler at the channel than GaN/SiC, backed by an US$18.2 million CHIPS award - but that route still uses diamond as a heat-spreading substrate, not an active device.

In China, the Ningbo Institute achieved 4-inch self-supporting diamond thin films by self-release in 2025 and extended MPCVD deposition area to 12 inches; Huanghe Whirlwind and Power Diamond are advancing 4-inch pilot production, though consistency and yield of electronic-grade single-crystal substrates remain the weak point.

6. How the future actually unfolds

Over the next 10–15 years, SiC and GaN will still dominate the power electronics market. For diamond to scale it must clear three gates at once: larger substrates, room-temperature n-type ionization efficiency, and standardised device processes.

Three things worth watching:

1. when 4-inch SCD substrates become reproducibly volume-producible;
2. whether room-temperature ionization efficiency in n-type doping can break through the 1% level;
3. whether the first commercial devices reach extreme-environment niche markets around 2030.

Its differentiation is in fact clear: ultra-high voltage (theoretically beyond 30 kV), extreme temperature (above 300 °C) and high-radiation environments. Nuclear decommissioning, space electronics, deep-space communications - these are applications that buy reliability rather than cost, and that is precisely diamond's window. It is no coincidence that one Japanese start-up entered through nuclear decommissioning and another through space.

In one line

What diamond lacks on its path from "ultimate heat-spreading material" to "ultimate semiconductor" is not proof of performance - that has long been settled. What it lacks is validation of an engineering path. Its position today is clear: substrate for heat first, power devices in extreme environments next, logic chips last. That missing n-type layer does not determine diamond's ceiling; it determines the timetable on which the industry gets to use it.

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Disclaimer: This article is adapted and rewritten from publicly available reports on the Chinese Internet and open scientific literature, provided for industry reference only. Bandgap, breakdown field, mobility, device metrics, substrate size and pricing figures cited herein come from published research, institutional reports and company disclosures; theoretical and measured values are labelled separately, and test conditions and device structures vary between sources. We make no representation as to their completeness, accuracy or timeliness, and this article does not constitute investment or procurement advice. For republication or citation, please contact huicetools and credit the original source.